1. Field of the Invention
The present invention generally relates to an analog-digital converter and, more particularly, to an analog-digital converter of a pipeline type and that of a cyclic type.
2. Description of the Related Art
In recent years, a variety of additional functions are built in mobile appliances such as a mobile telephone set, including the image pick-up function, the image playback function, the moving image pick-up function and the moving image playback function. In association with this, there is an increasing demand for miniaturization and power saving of an analog-digital converter (hereinafter, referred to as an AD converter). One mode of AD converter that addresses this demand is known as a cyclic AD converter which cycles through stages (see, for example, the Related art list No. 1).
FIG. 1 illustrates an example of a cyclic AD converter according to the related art. In this AD converter, an analog signal Vin input via a first switch SW1 is sampled and held by a sample and hold circuit 11 so that an analog signal equivalent to the input signal is held. An AD converter circuit 12 converts the signal thus held into a digital value. Initially, the higher 4 bits are retrieved. The digital value produced by conversion in the AD converter circuit 12 is converted into an analog value by a DA converter circuit 13. A subtracter circuit 14 subtracts the analog signal supplied from the DA converter circuit 13 from the input analog signal Vin sampled and held in the sample and hold circuit 11. An analog signal output from the subtracter circuit 14 is amplified by a second amplifier circuit 15. The amplified analog signal is fed back to the third sample and hold circuit 11 and the AD converter circuit 12 via a second switch SW2. 3 bits are retrieved in a second and subsequent cycles so that the second amplifier circuit 15 amplifies the input signal by a factor of 8. By repeating this process, a 10-bit digital value is obtained.
Related Art List
1. Japanese Patent Application Laid-open No. 4-26229
In the aforementioned AD converter of a cyclic type or the AD converter of a multiple-stage pipeline type, the higher bits are first retrieved and a corresponding analog signal is then subtracted from the input. Therefore, the analog signal after the subtraction should be amplified in accordance with the number of bits retrieved by the AD converter circuit in the subsequent stage.
However, the performance of an amplifier circuit is limited by a factor known as gain bandwidth product (GB product). The higher the target gain, the lower the operating frequency of the amplifier and the slower the operation. The operating speed equal to or higher than the overall speed of conversion is required in a cyclic type. Therefore, the amplifier circuit constitutes a limiting factor in the speed of operation of the AD converter as a whole.